1. Field of the Invention
This invention relates to a method for fabricating capacitors of a dynamic random access memory (DRAM), and more particularly, to a method for fabricating capacitors of a DRAM by using selective interlayer dielectric formation technology.
2. Description of Related Art
Referring to FIG. 1, it shows the circuit of a memory cell that comprises a MOS transistor T and a capacitor C within a DRAM, wherein the properties of charging and discharging on the capacitor can be used to store information. Generally, every digit in a binary information can be stored in a capacitor which will be charged is the stored digit is a logic 1, and a logic 0 if the capacitor is not charged. The source of the MOS transistor T is connected to a corresponding bit line BL, and the drain of the MOS transistor T is connected to the storage electrode (or lower electrode) 15 of the capacitor C, and the gate of the MOS transistor T is connected to a corresponding word line. The upper electrode is connected to a fixed voltage source. There is a dielectric layer 12 filled between the upper electrode 14 and lower electrodes 15 of the capacitor C.
Since the capacitor is the major device used by a memory cell for storing information. If the capacitance of the capacitor is high, the effect caused by noise will be reduced when a piece of information is read, and it will further reduce the frequency of refreshing.
A conventional method for fabricating cylinder capacitors of a DRAM is shown in FIGS. 2A through 2E. As referring to FIG. 2A, a field effect transistor is formed on the surface of a semiconductor substrate 200 such as a p-type silicon substrate, and the field effect transistor is isolated by field oxide 204, wherein the field effect transistor contains a gate 212, and source/drain 222 and 232. Then, an isolation layer 206 and an etching stop layer 216 are formed in sequence on the substrate 200. A contact hole is formed through the isolation layer and the etching stop layer for exposing the source/drain region 222 which is designed to be coupling with transistor, wherein the isolation layer 206 includes oxide, and the etching stop layer 216 includes silicon nitride. The contact hole is then filled with conducting material, such as polysilicon, to form a conductive plug 242.
Referring to FIG. 2B, a conductive layer 252 and a dummy oxide layer 226 are formed on the top of the etching stop layer 216 in sequence, and the bottom region of a lower electrode of the desired cylinder capacitor is defined and has contact with the conductive plug 242, wherein the conductive layer 252 includes doped polysilicon, and the dummy oxide layer 226 includes borophosphosilicate glass (BPSG) or phosphosilicate (PSG).
Referring to FIG. 2C, a conductive layer 262 is form for covering everything on the top of the substrate 200, wherein the conductive layer includes doped polysilicon.
Referring next to FIG. 2D, an anisotropic etching process is performed for forming the conductive spacers 262a, which is against the dummy oxide layer 226 and in contact with the conductive layer 252, by using the etching stop layer 216 as the etching ending, wherein the conductive spacers 262a and conductive layer 252 construct the lower electrode of the cylinder capacitor 272.
Referring next to FIG. 2E, the dummy oxide layer is removed by a wet etching method. A dielectric layer 236 having a thickness of approximate 10 .ANG..about.60 .ANG. is then formed on the exposed surface of the lower electrode of the cylinder capacitor 272, wherein the dielectric includes silicon oxide, silicon nitride/silicon oxide (NO) structure, silicon oxide/silicon nitride/silicon oxide (ONO) structure, or other dielectric materials of high permittivities such as Ta.sub.2 O.sub.5, Pb(Zr,Ti)O.sub.3 (i.e. PZT), or (Ba,Sr)TiO.sub.3 (i.e. BST).
After that, a conductive layer 282 is formed on the top surface of the dielectric layer 236 as the upper electrode of the cylinder capacitor for accomplishing the capacitor of a DRAM.
However, the conventional method for fabricating cylinder capacitors of a DRAM is too complicated, and the fabrication cost is not economical.